Typically, a computer system includes a number of integrated circuits that communicate with one another to perform system applications. Often, the computer system includes one or more host controllers and one or more electronic subsystem assemblies. To perform system functions, the host controller(s) and subsystem assemblies communicate via communication links, such as parallel communication links and serial communication links. Parallel communication links include links that implement conventional peripheral component interconnect (PCI), which is part of the PCI Local Bus standard, and PCI eXtended (PCI-X). Serial communication links include links that implement the PCI Express (PCIe) standard.
Conventional PCI is a bus for attaching hardware devices in a computer. The devices can take the form of an integrated circuit fitted onto the motherboard or an expansion card that fits into a slot. Typical PCI cards include: network cards, sound cards, modems, extra ports, television tuner cards, and disk controllers.
PCI-X is a bus and expansion card standard that enhances the PCI Local Bus standard for higher bandwidth demanded by servers. PCI-X revised the conventional PCI standard by doubling the maximum clock speed, from 66 MHz to 133 MHz. The theoretical maximum amount of data exchanged between the processor and peripherals with PCI-X is 1.06 GB/s, compared to 133 MB/s with standard PCI. Conventional PCI and PCI-X have largely been replaced by PCIe, which features a different logical design.
PCIe is used in consumer, server, and industrial applications as a motherboard-level interconnect to link motherboard-mounted peripherals and as an expansion card interface for add-in boards. A difference between PCIe and the earlier buses is a topology based on point-to-point serial links, rather than a shared parallel bus. PCIe is a high-speed, serial link that communicates data via differential signal pairs. A PCIe link is built around a bidirectional, serial, point-to-point connection referred to as a lane. At the electrical level, each lane utilizes two unidirectional low voltage differential signaling pairs, a transmit pair and a receive pair, for a total of four data wires per lane. A connection between any two PCIe devices is referred to as a link, and is built up from a collection of one or more lanes. All PCIe devices minimally support single-lane (x1) links. PCIe devices may optionally support wider links composed of x2, x4, x8, x12, x16, x32, or more lanes.
Typically, PCIe devices have storage locations, such as registers and memory locations, mapped into PCIe memory space, also referred to as memory mapped input/output (MMIO) space. Often, the MMIO space includes a portion addressable via 32-bit addresses and a portion addressable via 64-bit addresses. The portion addressable via 32-bit addresses, which addresses less than four giga-bytes (GB) of memory space, is referred to as LMMIO. The portion addressable via 64-bit addresses, which addresses greater than four GB of memory space, is referred to as GMMIO. The mapping resources in bridges and switches are defined to associate LMMIO space with non-prefetchable semantics, and GMMIO space with prefetchable semantics.
PCIe devices are requesting an increasingly large amount of non-prefetchable MMIO space. On highly scalable platforms that support a large number of PCIe devices, this can lead to a shortage of LMMIO space, which limits the number of devices that can be supported.
For these and other reasons there is a need for the present invention.